In a video tape recorder, a peak noise reduction circuit has been used for recording audio signals. The audio signals are recorded on a sound track of video tape after an FM modulation. Such a peak noise reduction circuit is used for expanding the dynamic range of the recorded signals through the FM modulation. For example, the dynamic range of recorded audio signals can be expanded to about a range of 90 dB suitable for a high-fidelity sound reproduction.
FIG. 1 shows an example of a typical peak noise reduction circuit for a video tape recorder. In FIG. 1, an input terminal 11 is provided for receiving an audio input signal to be recorded on a video tape. The audio input signal is applied to a division circuit 12. The division circuit 12 divides the audio input signal by a feedback signal, as described later. The divided signal obtained by the division circuit 12 is introduced to an output terminal 14 though a de-emphasis circuit 13. The output signal output from the de-emphasis circuit 13 is fed back to the division circuit 12 as the feedback signal through a waiting circuit 15 and a detection circuit 16.
The peak noise reduction circuit compresses the audio input signal to a half level in decibels (dB), as shown in FIG. 2. FIG. 2 shows the level compression characteristics of the peak noise reduction circuit. As shown in FIG. 2, an input level of the audio input signal is exponentially compressed. For example, an audio input signal input level of -6 dB is compressed to an output level of -3 dB.
The typical peak noise reduction circuit, as shown in FIG. 1, is constructed as an analog circuit. Recently, however, peak noise reduction circuits has been constructed as digital circuits. In a conventional digital peak noise reduction circuit, the de-emphasis circuit 13, the waiting circuit 15 and the detection circuit 16 of FIG. 1 can be constructed by conventional IIR (Infinite Impulse Response) filters. Further, the division circuit 12 of FIG. 1 has been conventionally constructed with digital circuits, as shown in FIG. 3.
In FIG. 3, first and second terminals 17 and 19 are provided for receiving a digital divisor Na and a digital dividend Nb, respectively. The divisor Na and the dividend Nb are supplied from the input terminal 11 and the detection circuit 16 of FIG. 1. The dividend Nb is applied to a multiplier 20. The divisor Na is applied to the multiplier 20 through an ROM (Read Only Memory) 18. The ROM 18 changes the divisor Na to data Nc relating to a reciprocal of the divisor Na. That is, the divisor Na is applied to the ROM 18 as address data so that the ROM 18 outputs a prescribed reciprocal data corresponding to the divisor Na supplied thereto as the address.
Data stored in the ROM 18 are multiplied into twice the real reciprocals of the divisors. Thus, the prescribed reciprocal data Nc multiplied by two is read out from the ROM 18 in response to the address data or the divisor Na supplied from the first input terminal 17. Such a multiplied reciprocal data Nc will be referred to as a modified reciprocal, hereinafter. The modified reciprocal Nc corresponds directly to the divisor Na supplied from the first input terminal 17.
The modified reciprocal Nc output from the ROM 18 is applied to the multiplier 20. The multiplier 20 multiplies the dividend Nb supplied from the second input terminal 19 with the modified reciprocal Nc. The result of multiplication Nd between the dividend Nb and the modified reciprocal Nc is applied to a shifter 21. The shifter 21 shifts the multiplication result Nd output from the multiplier 20 by a prescribed amount. In other words, the shifter 21 multiplies the multiplication result Nd by a prescribed fixed amount.
It is assumed that the dividend Nb and the divisor Na are digital signals of 16 bits and 8 bits, respectively. Accordingly, the divisor, i.e., the address Na of the ROM 18 and the modified reciprocal Nc corresponding to the address Na are represented as binary data from [0] to [255]. If the address Na is [128], the ROM 18 outputs a binary data [2] as the modified reciprocal Nc of the address Na, [128].
Here, the real reciprocal of the binary data [128] is [1/128]. The real reciprocal [1/128] can be obtained as follows. The modified reciprocal Nc with the binary data [2] is applied to the multiplier 20. The multiplier 20 multiplies the dividend Nb supplied from the second input terminal 19 by the modified reciprocal Nc, i.e., the binary data [2]. The dividend Nb is converted to a multiplication resultant Nd, i.e., a binary data of Nb.times.[2]. The multiplication resultant Nd is applied to the shifter 21. The shifter 21 shifts the multiplication resultant Nd by a prescribed amount. In other words, the shifter 21 further multiplies the multiplication resultant Nd by a prescribed amount.
For example, if the amount of shift operation carried out by the shifter 21 is set to [1/256], the shifter 21 further multiplies the multiplication resultant Nd by the amount of shift [1/256]. As a result, division data Ne represented as follows is obtained from the shifter 21. ##EQU1##
The division data Ne is applied to the de-emphasis circuit 13, as shown in FIG. 1, through an output terminal 22 of the division circuit of FIG. 2. The division data Ne corresponds to a quotient between the dividend Nb and the divisor Na with the binary data [128].
The dividend Nb and the divisor Na are binary data with 16 bits and 8 bits, respectively, as described above. Thus, the multiplication resultant Nd obtained by the series circuit of the multiplier 20 and the shifter 21 is converted to 10 bit binary data.
FIG. 4 shows the conversion characteristics of the ROM 18 for outputting the modified reciprocal Nc. As shown in FIG. 4, the divisors Na such as [255], [128], [64], [32], . . . are converted to the corresponding modified reciprocals Nc [1], [2], [4], [8], . . . The modified reciprocals Nc [1], [2], [4], [8]. . . are applied to the multiplier 20. Then, the quotients, i.e., the multiplication resultants Nd such as Nb.times.[1/255], Nb.times.[1/128], Nb.times.[1/64], Nb.times.[1/32]. . . are obtained from the output terminal 22.
The conventional division circuit suitable for peak noise reduction circuits has a drawback as described below. That is, the ROM has a variable resolution for changing the divisor Na to the modified reciprocal Nc. For example, the modified reciprocal Nc varies in a range between [255] and [128] in response to the change of the divisor Na between a range between [1] and [2]. In the range of the divisor change between [1] and [2], the ROM 18 has a relatively high resolution [128] ([255].fwdarw.[128]) for modified reciprocal Nc. The resolution of the ROM 18 decreases to [64] ([128].fwdarw.[64]), in the range of the divisor change between [2] and [4]. Thus, the resolution of the ROM 18 abruptly decreases in the order of [32], [16], [8], [4], [2], [1], in response to the increase of the divisor Na in the order of [8], [16], [32], [64], [128], [256].
The conversion characteristics of the ROM 18 influence the compression characteristics of the digital peak noise reduction circuit. If it is assumed that filters constituting the de-emphasis circuit 13, the waiting circuit 15 and the detection circuit 16 of FIG. 1 commonly have a gain [1], the digital peak noise reduction circuit has a compression characteristic, as shown in FIG. 5. As shown in FIG. 5, the resolution of the digital peak noise reduction circuit abruptly drops with increases in the level of the digital input signal.